The use of photolithography in the fabrication of semiconductor integrated circuits is well-established in the industry. Such techniques involve covering the semiconductor substrate with a photoresist material, exposing the photoresist to light through a mask including a desired pattern, and developing the photoresist so that the pattern is formed in the resist. The semiconductor can then be etched or materials deposited using the photoresist as a mask.
One of the challenges in this technology is to control feature sizes in the photoresist when the semiconductor substrate has a varying topology. For example, photoresist material is often formed over an existing gate oxide pattern on the substrate. Light incident on the photoresist which is reflected by the gate over thicker portions of oxide will travel a shorter distance than light reflected by the thinner oxide portions. These reflected rays, therefore, will form different interference patterns with light reflected by the top of the photoresist layer, thereby causing a variation in the intensity of light exposing the photoresist. The variations in exposure cause variations in the dimensions of the features defined by the photoresist.
One recent proposal for solving these problems involves forming an anti-reflection coating having a variable index of refraction over the semiconductor substrate. In one embodiment, the anti-reflection coating is made of a silicon-containing oxide with the index of refraction varied by varying the amount of silicon relative to the amount of oxide. (See U.S. Patent Application of Cirelli and Weber, Ser. No. 08/611595, filed on Mar. 7, 1996, now abandoned which is incorporated by reference herein.)
Building on this teaching, what is desired are anti-reflection coating stacks which provide optimum reflectivity control for various circuit topologies.